Currently, the MEMS dual-axis mirrors involve a precision spacer and electrode layer. This has been done by multiple wafer bonding process, resulting in poor manufacturing yield. The invention replaces the spacer-electrode stack with one spacer-VIA substrate. This process allows a variety of bonding methods for the subsequent processes, thus reducing the complexity of the fabrication process and improving the overall yield. The MEMS technology finds its applications in optics in which a small-size mirror (micromirror) in the order of 10 μm to 500 μm can be actuated by applied voltages. There are numerous prior arts on the mirror structures (found citations). In general, two-axis mirrors are more useful because the mirrors can steer the optical beam in two dimensions. Usually, these designs involve double hinges with gimble. There are two classes of actuator designs. The first class is to have the actuators on the same surface of the MEMS mirror layer but outside the optical region. Examples of these types of actuators include comb drive or thermal actuators. The second class is to have the actuator underneath the MEMS mirrors. These types of actuators are, in general, electrostatic. The structures of the second class is more commonly adopted in the applications requiring high-fill-factor and/or high-density mirrors. One example of these is described in U.S. Pat. No. 6,984,917 and is illustrated in FIG. 1.
As shown in FIG. 1, a mirror 1 and frame 2 are formed from a common sheet of material. The mirror 1 is connected to the frame 2 by a thin member 3 formed from the sheet of material. The thin member 3 lies along an axis of rotation that lies perpendicular to the plane of the drawing in FIG. 1. The thin member 3 acts as a torsional spring hinge. The mirror 1 is suspended over cavity 4 so that it is free to rotate. Electrodes 5A and 5B are disposed in the cavity 4. Electrodes 5A and 5B underlie a portion of the mirror 1, with one electrode on each side of an axis-of-rotation defined by the thin member 3.
When an electrical potential is applied between a mirror 1 and one of the underlying electrodes 5A, 5B, the cradle rotates out-of-plane, i.e., out of the plane defined by the support frame 2, about its axis of rotation toward the electrified electrode. Torsional forces developed by the thin member 3 tend to counteract the electrostatic force between the attractive electrode and cradle. The mirror 1 can rotate about the axis defined by the thin member 3 by an angle φ that depends on the voltages applied to the electrified electrode the separation of the mirror and the electrode and the torsional stiffness of the hinge. The direction of rotation depends on which electrode is electrified. For example, if an electric potential is applied between mirror 1 and electrode 5B, mirror 1 rotates out-of-plane of frame 2 about axis X such that the portion of mirror 1 that overlies electrode 5B moves downward toward that electrode.
In a device of the type shown in FIG. 1, the electrodes 5A and 5B should be electrically isolated from each other to avoid large currents between them when a voltage is applied. In fact, in order to allow the mirror to tilt in both clockwise and counterclockwise in FIG. 1, two electrodes are needed. For dual-axis operation, 3 or 4 electrodes are needed. To ease the control algorithm, 4 electrodes per mirror are often employed.
Since the device is operated by electrostatic force, a physical gap between the electrodes and the mirror is very critical. This gap needs to be controlled with high precision to ensure the performance of the device. Typically, with a smaller gap, less voltage is needed to tilt the mirror to a certain angle. However, the maximum angle (before a snapping behavior occurs) is smaller. With a larger gap, higher voltage is needed to tilt the mirror to a certain angle, but the maximum angle is also enlarged. Therefore, there exists an optimal gap for each application.
While a through-wafer interconnect is commercially available, an integrated solution is not available without this integrated spacer. In order to access the electrodes underneath the MEMS mirror, a dedicated electrode layer is used to bring the electrical contact to a region with no MEMS mirror, followed by an access etch from the top structure. This consumes a significant portion of the area of the wafer on which MEMS mirrors are formed, reducing the number of dies per wafer. Using commercially available vias or through-wafer interconnects can change the interconnect direction from lateral to vertical. However, it does not integrate a spacer layer with sufficient thickness accuracy for the device operation. It turns out that combining an integrated spacer with a vertical interconnect substrate provides a large degree of process latitude. Competitors will have to build a spacer layer on top of the VIA wafer. The choice of the processes and materials will limit the choices of the subsequent process.
For example, if an organic material is selected, the subsequent process temperature will be limited.
In many applications, high density of micromirrors is required, either in 1×N or N×M format. The number of the mirrors increases the number of the controlling electrodes. For dual-axis operation, three or four electrodes may be needed for each micromirror. Therefore, for example, for a 10×10 micromirror array, the number of electrodes can be as large as 300 to 400.
As seen in FIG. 1, the electrodes are under the micromirrors. Therefore, there must be an electrical connection (interconnect) between the bond pads to the electrodes. In most cases, the size of the bond pads is larger than the size of the micromirrors. This causes the useable area of the overall die to be a small fraction of the entire die area, thus greatly reducing the number of dies per wafer. As an example to illustrate this issue, FIG. 2 shows a top view of a MEMS 1×N micromirror array. Since the pitch of the micromirrors is typically narrower than the pitch of the bond pads for standard wire bonding process, a fan-out-shaped interconnect region 6 is used to electrically connect an optical region 7 and a bond pad region 8. As may be seen from FIG. 2, the real estate of a MEMS wafer is not fully utilized by this approach. One approach to resolve the foregoing real estate issue is to perform the interconnect in the vertical direction by putting the electrode contacts of the bond pad region 8 on the backside of the MEMS wafer with electrical connection to the driver electronics by a solder bump process. The solder bump process, developed for flip-chip assembly for Silicon (Si) CMOS, offers a much higher interconnect density. In order to bring the electrical contact vertically, it is possible to integrate a commercially available through-wafer interconnect technology. Examples of such interconnect technology are described, e.g., in U.S. Patent Application Publications Numbers 20080122031, 20080157339, and 20080157361, which are incorporated herein by reference.
A typical through-wafer interconnect is shown in FIG. 3. The through-wafer interconnect technology may also be made by a standard MEMS fabrication process. First, through holes may be formed through a substrate 9, such as a Silicon (Si) wafer, followed by depositing insulating passivation layer 10 on the sidewalls of the holes. Then, a conducting material 11 is used to fill the remaining holes. The holes may be formed by an anisotropic etch process such as Deep Reactive Ion Etching (DRIE). The insulating passivation layer is typically thermally grown SiO2. But, other deposition techniques (PECVD, CVD) may also be used.
The choices of the conducting materials are based on the applications. For applications in which conductivity is important, electroplated metals are commonly used. If low conductivity is acceptable, poly silicon is commonly used for the benefit of similar thermal expansion coefficient with the substrate.
An example of a MEMS micro-gyroscope using a through-wafer interconnect described in U.S. Pat. No. 7,015,060 to Kubena, which is incorporated herein by reference, is shown in FIG. 4. The gyroscope is formed using four wafers. A resonator 23 is formed from a top silicon layer of a silicon-on-insulator (SOI) wafer. A post 12 is formed from a bottom silicon layer of the SOI wafer. A second wafer bonded to the first wafer is used to form another post 13. A third wafer 14 having a silicon substrate 15 is etched to form pillars and through holes. The substrate 15 is oxidized to coat its front and back surfaces and line the walls of the through holes with a layer of SiO2 16. Electrically conductive interconnects 17 are formed by filling the through holes with metal. In this case, electroplated copper or copper alloy were preferred for the conducting material owing to the electrical requirements of the device. Metal is formed over the pillars and interconnects 17 and patterned to form electrodes connected to the interconnects. A hole is then made in the third wafer 14 to receive the post 13. The resonator 23 is then bonded to the third wafer 14 at the metal on the pillars. A cavity 18 is formed in a base layer 19 of a fourth wafer 20 (another SOI wafer) to accommodate the resonator 23 and post 12. The fourth wafer 20 is then bonded to the third wafer 14 using a sealing ring metal 21 and a solder 22. The fourth wafer 20 acts as a cap for the resonator 23. As seen in FIG. 4, the through-wafer interconnect is much more complicated than that in FIG. 2. This is because it is not straightforward to integrate the vertical interconnect concept directly to the various operating modes of MEMS devices.
Specifically, if a MEMS mirror device of the type shown in FIG. 1 were to be combined with a vertical through-wafer interconnect, the mirror, it would be desirable to precisely control the spacing between the layer from which the mirror is formed and the electrodes located underneath the mirror and on top of the through-wafer interconnects. Unfortunately, such precision is difficult to obtain with high yield using a process like that described in U.S. Pat. No. 7,015,060.
There are also challenges to utilizing through-wafer interconnects in a micromirror array application. These challenges include, e.g., the density of the interconnect, the locations of electrode, and the requirements for precision for the gap between the electrodes and the mirrors. The pitch of the micromirror array typically is between 50 μm to 500 μm. The pitch of the standard solder bump process is typically around 200 μm. If 4 electrodes are needed for each mirror, clearly some form of routing is required to distribute the electrodes from the patterns, required by the operation of the MEMS devices, to the contact patterns acceptable for the solder bump process.
It is within this context that embodiments of the present invention arise.